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Features
www..com * Low-voltage and Standard-voltage Operation
* * * * * * * * * *
* * *
- 2.7 (VCC = 2.7 to 5.5V) - 1.8 (VCC = 1.8 to 5.5V) Low-power Devices (ISB = 6 A at 5.5V) Available Internally Organized 8192 x 8 2-Wire Serial Interface Schmitt Trigger, Filtered Inputs for Noise Suppression Bi-directional Data Transfer Protocol 400 kHz Clock Rate Write Protect Pin for Hardware Data Protection 32-Byte Page Write Mode (Partial Page Writes Allowed) Self-Timed Write Cycle (5 ms max) High Reliability - Endurance: 1 Million Write Cycles - Data Retention: 100 Years Lead-free/Halogen-free Devices Available 8-lead JEDEC SOIC and 8-lead TSSOP Packages Die Sales: Wafer Form, Waffle Pack, and Bumped Wafers
2-Wire Serial EEPROM
64K (8192 x 8)
AT24C64B
Description
The AT24C64B provides 65,536 bits of serial electrically erasable and programmable read only memory (EEPROM) organized as 8192 words of 8 bits each. The device's cascadable feature allows up to 8 devices to share a common 2-wire bus. The device is optimized for use in many industrial and commercial applications where low power and low voltage operation are essential. The AT24C64B is available in space saving 8-lead JEDEC SOIC and 8-lead TSSOP packages and is accessed via a 2-wire serial interface. In addition, the entire family is available in 2.7V (2.7 to 5.5V) and 1.8V (1.8 to 5.5V) versions.
Pin Configurations
Pin Name A0 - A2 SDA SCL WP Function Address Inputs Serial Data Serial Clock Input Write Protect
A0 A1 A2 GND
8-lead SOIC
1 2 3 4 8 7 6 5 VCC WP SCL SDA
2-Wire, 32K Serial E2PROM
8-lead TSSOP
A0 A1 A2 GND 1 2 3 4 8 7 6 5 VCC WP SCL SDA
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Absolute Maximum Ratings*
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Operating Temperature...................................... -55 to +125C Storage Temperature ......................................... -65 to +150C Voltage on Any Pin with Respect to Ground ....................................... -1.0 to +7.0V Maximum Operating Voltage .......................................... 6.25V DC Output Current........................................................ 5.0 mA
*NOTICE:
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
1. Block Diagram
VCC GND WP SCL SDA START STOP LOGIC
LOAD DEVICE ADDRESS COMPARATOR A2 A1 A0 R/W COMP
SERIAL CONTROL LOGIC
EN
H.V. PUMP/TIMING
DATA RECOVERY INC X DEC EEPROM
LOAD
DATA WORD ADDR/COUNTER
Y DEC
SERIAL MUX
DIN DOUT
DOUT/ACK LOGIC
2. Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device. SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open collector devices. DEVICE/ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address inputs that are hard wired or left not connected for hardware compatibility with other AT24CXX devices. When the pins are hardwired, as many as eight 64K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section). If the pins are left floating, the A2, A1 and A0 pins will be internally pulled down to GND if the capacitive cou-
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pling to the circuit board VCC plane is <3pF. If coupling is >3pF, Atmel recommends connecting the address pins to GND. WRITE PROTECT (WP): The write protect input, when connected to GND, allows normal write operations. When WP is connected high to VCC, all write operations to the upper quandrant (16K bits) of memory are inhibited. If the pin is left floating, the WP pin will be internally pulled down to GND if the capacitive coupling to the circuit board VCC plane is <3pF. If coupling is >3pF, Atmel recommends connecting the pin to GND.
3. Memory Organization
AT24C64B, 64K SERIAL EEPROM: The 64K is internally organized as 256 pages of 32 bytes each. Random word addressing requires a 13 bit data word address.
Pin Capacitance(1)
Applicable over recommended operating range from TA = 25C, f = 1.0 MHz, VCC = +1.8V
Symbol CI/O CIN Note: Test Condition Input/Output Capacitance (SDA) Input Capacitance (A0, A1, A2, SCL) 1. This parameter is characterized and is not 100% tested. Max 8 6 Units pF pF Conditions VI/O = 0V VIN = 0V
DC Characteristics
Applicable over recommended operating range from: TAI = -40 to +85C, VCC = +1.8 to +5.5V (unless otherwise noted)
Symbol VCC1 VCC2 VCC3 ICC1 ICC2 ISB1 ISB2 ISB3 ILI ILO VIL VIH VOL2 VOL1 Note: Parameter Supply Voltage Supply Voltage Supply Voltage Supply Current Supply Current Standby Current (1.8V option) Standby Current (2.7V option) Standby Current (5V option) Input Leakage Current Output Leakage Current Input Low Level(1) Input High Level
(1)
Test Condition
Min 1.8 2.7 4.5
Typ
Max 5.5 5.5 5.5
Units V V V mA mA A A A A A V V V V
VCC = 5.0V VCC = 5.0V VCC = 1.8V VCC = 2.7V VCC = 4.5 - 5.5V VIN = VCC or VSS VOUT = VCC or VSS
READ at 400 kHz WRITE at 400 kHz VIN = VCC or VSS VIN = VCC or VSS VIN = VCC or VSS
0.4 2.0
1.0 3.0 1.0 2.0 6.0
0.10 0.05 -0.6 VCC x 0.7
3.0 3.0 VCC x 0.3 VCC + 0.5 0.4 0.2
Output Low Level Output Low Level
VCC = 3.0V VCC = 1.8V
IOL = 2.1 mA IOL = 0.15 mA
1. VIL min and VIH max are reference only and are not tested.
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4. AC Characteristics
Applicable over recommended operating range from TAI = -40C to +85C, VCC = +1.8V to +5.5V, CL = 1 TTL Gate and 100 pF (unless otherwise noted)
AT24C64B 1.8V - 3.6V Symbol fSCL tLOW tHIGH tI tAA tBUF tHD.STA tSU.STA tHD.DAT tSU.DAT tR tF tSU.STO tDH tWR Endurance
) (1
5.0V Min Max 400 1.2 0.6 Units kHz s s 50 0.1 1.2 0.6 0.6 0 100 0.9 ns s s s s s ns 0.3 300 0.6 50 s ns s ns 5 1M ms Write Cycles
Parameter Clock Frequency, SCL Clock Pulse Width Low Clock Pulse Width High Noise Suppression Time
(1)
Min
Max 400
1.3 0.6 100 0.2
(2)
Clock Low to Data Out Valid Time the bus must be free before a new transmission can start Start Hold Time Start Set-up Time Data In Hold Time Data In Set-up Time Inputs Rise Time
(2)
0.9
1.3 0.6 0.6 0 100 0.3 300 0.6 200 5 1M
Inputs Fall Time(2) Stop Set-up Time Data Out Hold Time Write Cycle Time 5.0V, 25C, Page Mode
Notes:
1. This parameter is characterized and is not 100% tested (TA = 25C) 2. This parameter is characterized and is not 100% tested.
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5. Device Operation
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CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (refer to Data Validity timing diagram). Data changes during SCL high periods will indicate a start or stop condition as defined below. START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (refer to Start and Stop Definition timing diagram). STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (refer to Start and Stop Definition timing diagram). ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to acknowledge that it has received each word. STANDBY MODE: The AT24C64B features a low power standby mode which is enabled: a) upon power-up and b) after the receipt of the Stop bit and the completion of any internal operations. MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2-wire part can be reset by following these steps: (a) Clock up to 9 cycles, (b) look for SDA high in each cycle while SCL is high and then (c) create a start condition as SDA is high.
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6. Bus Timing www..com SCL: Serial Clock, SDA: Serial Data I/O
tF tHIGH tLOW tR
SCL
tSU.STA tHD.STA
tLOW
tHD.DAT
tSU.DAT
tSU.STO
SDA IN
tAA tDH tBUF
SDA OUT
7. Write Cycle Timing SCL: Serial Clock, SDA: Serial Data I/O
SCL
SDA
8th BIT
ACK
WORDn twr STOP CONDITION
Note:
(1)
START CONDITION
1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.
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8. Data Validity
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SDA
SCL DATA STABLE DATA CHANGE DATA STABLE
9. Start and Stop Definition
SDA
SCL
START
STOP
10. Output Acknowledge
SCL
1 8 9
DATA IN
DATA OUT
START
ACKNOWLEDGE
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11. Device Addressing
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The 64K EEPROM requires an 8-bit device address word following a start condition to enable the chip for a read or write operation (see Figure 13-1 on page 11). The device address word consists of a mandatory one, zero sequence for the first four most significant bits as shown. This is common to all 2-wire EEPROM devices. The 64K uses the three device address bits A2, A1, A0 to allow as many as eight devices on the same bus. These bits must compare to their corresponding hardwired input pins. The A2, A1, and A0 pins use an internal proprietary circuit that biases them to a logic low condition if the pins are allowed to float. The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low. Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the device will return to standby state. NOISE PROTECTION: Special internal circuitry placed on the SDA and SCL pins prevent small noise spikes from activating the device. A low-VCC detector (5-volt option) resets the device to prevent data corruption in a noisy environment. DATA SECURITY: The AT24C64B has a hardware data protection scheme that allows the user to write protect the upper quadrant (16K bits) of memory when the WP pin is at VCC.
12. Write Operations
BYTE WRITE: A write operation requires two 8-bit data word addresses following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a zero and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally-timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (see Figure 13-2 on page 11). PAGE WRITE: The 64K EEPROM is capable of 32-byte page writes. A page write is initiated the same way as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to 31 more data words. The EEPROM will respond with a zero after each data word received. The microcontroller must terminate the page write sequence with a stop condition (see Figure 13-3 on page 11). The data word address lower 5 bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than 32 data words are transmitted to the EEPROM, the data word address will "roll over" and previous data will be overwritten. ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a zero, allowing the read or write sequence to continue.
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13. Read Operations
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Read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to one. There are three read operations: current address read, random address read and sequential read. CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address "roll over" during read is from the last byte of the last memory page, to the first byte of the first page. The address "roll over" during write is from the last byte of the current page to the first byte of the same page. Once the device address with the read/write select bit set to one is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input zero but does generate a following stop condition (see Figure 13-4 on page 12). RANDOM READ: A random read requires a "dummy" byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a zero but does generate a following stop condition (see Figure 13-5 on page 12). SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will "roll over" and the sequential read will continue. The sequential read operation is terminated when the microcontroller does not respond with a zero but does generate a following stop condition (see Figure 13-6 on page 12).
Figure 13-1. Device Address
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Figure 13-2. Byte Write
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Figure 13-3. Page Write
Note:
1. * = DON'T CARE bits
Figure 13-4. Current Address Read
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Figure 13-5. Random Read
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Note:
1. * = DON'T CARE bits
Figure 13-6. Sequential Read
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AT24C64B Ordering Information(1)
Ordering Code AT24C64BN-10SU-2.7 AT24C64BN-10SU-1.8(2) AT24C64B-10TU-2.7(2) AT24C64B-10TU-1.8(2) AT24C64B-W1.8-11(3) Notes:
(2)
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Package 8S1 8S1 8A2 8A2 Die Sale
Operation Range Lead-free/Halogen-free Industrial Temperature (-40C to 85C) Industrial Temperature (-40C to 85C)
1. For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics tables. 2. "U" designates Green Package & RoHS compliant. 3. Available in waffle pack and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please contact Serial Marketing.
Package Type 8S1 8A2 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8-lead, 4.4 mm Body, Plastic, Thin Shrink Small Outline Package (TSSOP) Options -2.7 -1.8 Low Voltage (2.7V to 5.5V) Low Voltage (1.8V to 5.5V)
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14. Packaging Information
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8S1 - JEDEC SOIC
C
1
E
E1
N
L
O
TOP VIEW END VIEW
e b A A1
SYMBOL A A1 b C COMMON DIMENSIONS (Unit of Measure = mm) MIN 1.35 0.10 0.31 0.17 4.80 3.81 5.79 NOM - - - - - - - 1.27 BSC 0.40 0 - - 1.27 8 MAX 1.75 0.25 0.51 0.25 5.05 3.99 6.20 NOTE
D
D E1
SIDE VIEW
E e L
Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
3/17/05 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) DRAWING NO. 8S1 REV. C
R
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8A2 - TSSOP
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3
21
Pin 1 indicator this corner
E1
E
L1
N L
Top View
End View
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN 2.90 NOM 3.00 6.40 BSC 4.30 - 0.80 0.19 4.40 - 1.00 - 0.65 BSC 0.45 0.60 1.00 REF 0.75 4.50 1.20 1.05 0.30 4 3, 5 MAX 3.10 NOTE 2, 5
b
A
D E E1 A
e D
A2
A2 b e
Side View
L L1
Notes:
1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc. 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07 mm. 5. Dimension D and E1 to be determined at Datum Plane H. 5/30/02
R
2325 Orchard Parkway San Jose, CA 95131
TITLE 8A2, 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)
DRAWING NO. 8A2
REV. B
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Revision History
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Doc. Rev. 3350E
Date 9/2007
Comments Updated to new template; implemented revision history.
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Headquarters
Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600
International
Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581
Product Contact
Web Site www.atmel.com Technical Support s_eeprom@atmel.com Sales Contact www.atmel.com/contacts
Literature Requests www.atmel.com/literature
Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL'S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL'S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel's products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.
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